Iridium, the most widely used anode catalyst in proton exchange membrane water electrolysis (PEMWE), must be used minimally due to its high price and limited supply. However, reducing iridium loading poses challenges due to abnormally large anode polarization. Herein, we present an anode catalyst layer (CL) based on a one-dimensional iridium nanofiber that enables a high current density operation of 3 A cm-2 at 1.86 V, even at an ultralow loading (0.07 mgIr cm-2). The performance is maintained even with a Pt coating-free porous transport layer (PTL) because our nanofiber CL circumvents the interfacial electron transport problem caused by the native oxide on the Ti PTL. We attribute this to the low work function and the low-ionomer-exposed surface of the nanofiber CL, which prevent the formation of Schottky contact at the native oxide interface. These results highlight the significance of optimizing the electronic properties of the CL/PTL interface for low-iridium-loading PEMWE.

Atomically precise graphene nanoribbons (GNRs) synthesized from the bottom-up exhibit promising electronic properties for high-performance field-effect transistors (FETs). The feasibility of fabricating FETs with GNRs (GNRFETs) has been demonstrated, with ongoing efforts aimed at further improving their performance. However, their long-term stability and reliability remain unexplored, which is as important as their performance for practical applications. In this work, we fabricated short-channel FETs with nine-atom-wide armchair GNRs (9-AGNRFETs). We revealed that the on-state (ION) current performance of the 9-AGNRFETs deteriorates significantly over consecutive full transistor on and off logic cycles, which has neither been demonstrated nor previously considered. To address this issue, we deposited a thin ∼10 nm thick atomic layer deposition (ALD) layer of aluminum oxide (Al2O3) directly on these devices. The integrity, compatibility, electrical performance, stability, and reliability, of the GNRFETs before and/or after Al2O3 deposition were comprehensively studied. The results indicate that the observed decline in electrical device performance is most likely due to the degradation of contact resistance over multiple measurement cycles. We successfully demonstrated that the devices with the Al2O3 layer operate well up to several thousand continuous full cycles without any degradation. Our study offers valuable insights into the stability and reliability of GNR transistors, which could facilitate their large-scale integration into practical applications.

The imperfect charge behavior at the interfaces of perovskite/electron-transport layer (ETL)/transparent conducting oxide (TCO) limits the further performance improvement of perovskite/silicon tandem solar cells. Herein, an indium tin oxide interlayer is deposited between ETL and TCO to address this issue. Specifically, the interlayer is prepared using an all-physical and H2O-free method, electron-beam evaporation, which can avoid any potential damage to the underlying perovskite and ETL layers. Moreover, the interlayer\'s composition can be readily tuned by changing the evaporator component, enabling authors to regulate the contact resistance and energy-level alignment of the ETL/TCO interface. Consequently, the resultant perovskite/silicon tandem solar cells exhibit an impressive power conversion efficiency (PCE) of 30.8% (certified 30.3%). Moreover, the device retains 98% of its initial PCE after continuous operation under ambient conditions for 1078 h, representing one of the most stable and efficient perovskite/silicon tandem solar cells.

For N-type tunnel-oxide-passivated-contact silicon solar cells, optimal Ag/Al-Si contact interface is crucial to improve the efficiency. However, the specific roles of Ag and Al at the interface have not been clearly elucidated. Hence, this work delves into the sintering process of Ag/Al paste and examines the impact of the Ag/Al-Si interface structure on contact quality. By incorporating TeO2 into PbO-based Ag/Al paste, the Ag/Al-Si interface structure can be modulated. It can be found that TeO2 accelerates the sintering of Ag powder and increases Ag colloids within glass layer, while it simultaneously impedes the diffusion of molten Al. It leads to a reduced Al content near the Ag/Al-Si interface and a shorter diffusion distance of Al into Si. Notably, it can be demonstrated that the diffusion of Al in Si layer is more effective to reduce the contact resistance than the precipitation of Ag colloids. Therefore, the PbO-based Ag/Al paste, which favors Al diffusion, leads to solar cells with lower contact resistance and series resistance, higher fill factor, and superior photoelectric conversion efficiency. In brief, this work is significant for optimizing metallization of silicon solar cells and other semiconductor devices.

Microelectromechanical systems (MEMS) ohmic contact switches are considered to be a promising candidate for wireless communication applications. The longevity of MEMS switches is directly related to the reliability and performance of microcontacts. In this work, an improved microcontact test fixture with high actuation rates (KHz) and highly precise position control (nm) and force (nN) control was developed. Here, we collected microcontact performance data from initial contact tests (ICT) and microcontact reliability data from cold switched tests (CST). To perform these tests with our test fixture, we fabricated MEMS microcontact test structures with relatively high Young\'s modulus electroplated Nickel (Ni)-based, fixed-fixed beam structure with Au/RuO2 bimetallic microcontacts. These structures were characterized for forces ranging from 200-1000 µN in ICT tests. In a CST test, the tested microcontact survived more than 200 million cycles at a 1 KHz cycle rate, with a stable contact resistance value ranging between 3.8-5.2 Ω. These experiments validate the potentiality of our microcontact test fixture, and will facilitate further investigation on advanced microcontacts to enhance the MEMS switch\'s reliability.

Contact resistance is a multifaceted challenge faced by the 2D materials community. Large Schottky barrier heights and gap-state pinning are active obstacles that require an integrated approach to achieve the development of high-performance electronic devices based on 2D materials. In this work, we present semiconducting PtSe2 field effect transistors with all-van-der-Waals electrode and dielectric interfaces. We use graphite contacts, which enable high ION/IOFF ratios up to 109 with currents above 100 μA μm-1 and mobilities of 50 cm2 V-1 s-1 at room temperature and over 400 cm2 V-1 s-1 at 10 K. The devices exhibit high stability with a maximum hysteresis width below 36 mV nm-1. The contact resistance at the graphite-PtSe2 interface is found to be below 700 Ω μm. Our results present PtSe2 as a promising candidate for the realization of high-performance 2D circuits built solely with 2D materials.

The pursuit of sub-1-nm field-effect transistor (FET) channels within 3D semiconducting crystals faces challenges due to diminished gate electrostatics and increased charge carrier scattering. 2D semiconductors, exemplified by transition metal dichalcogenides, provide a promising alternative. However, the non-idealities, such as excess low-frequency noise (LFN) in 2D FETs, present substantial hurdles to their realization and commercialization. In this study, ideal LFN characteristics in monolayer MoS2 FETs are attained by engineering the metal-2D semiconductor contact and the subgap density of states (DOS). By probing non-ideal contact resistance effects using CuS and Au electrodes, it is uncovered that excess contact noise in the high drain current (ID) region can be substantially reduced by forming a van der Waals junction with CuS electrodes. Furthermore, thermal annealing effectively mitigates sulfur vacancy-induced subgap density of states (DOS), diminishing excess noise in the low ID region. Through meticulous optimization of metal-2D semiconductor contacts and subgap DOS, alignment of 1/f noise with the pure carrier number fluctuation model is achieved, ultimately achieving the sought-after ideal LFN behavior in monolayer MoS2 FETs. This study underscores the necessity of refining excess noise, heralding improved performance and reliability of 2D electronic devices.

The potential of monolithic 3D integration technology is largely dependent on the enhancement of interconnect characteristics which can lead to thinner stacks, better heat dissipation, and reduced signal delays. Carbon materials such as graphene, characterized by sp2 hybridized carbons, are promising candidates for future interconnects due to their exceptional electrical, thermal conductivity and resistance to electromigration. However, a significant challenge lies in achieving low contact resistance between extremely thin semiconductor channels and graphitic materials. To address this issue, an innovative wafer-scale synthesis approach is proposed that enables low contact resistance between dry-transferred 2D semiconductors and the as-grown nanocrystalline graphitic interconnects. A hybrid graphitic interconnect with metal doping reduces the sheet resistance by 84% compared to an equivalent thickness metal film. Furthermore, the introduction of a buried graphitic contact results in a contact resistance that is 17 times lower than that of bulk metal contacts (>40 nm). Transistors with this optimal structure are used to successfully demonstrate a simple logic function. The thickness of active layer is maintained within sub-7 nm range, encompassing both channels and contacts. The ultrathin transistor and interconnect stack developed here, characterized by a readily etchable interlayer and low parasitic resistance, leads to heterogeneous integration of future 3D integrated circuits (ICs).

Two-dimensional (2D) transitional metal dichalcogenides (TMDs) have garnered significant attention due to their potential for next-generation electronics, which require device scaling. However, the performance of TMD-based field-effect transistors (FETs) is greatly limited by the contact resistance. This study develops an effective strategy to optimize the contact resistance of WSe2 FETs by combining contact doping and 2D metallic electrode materials. The contact regions were doped using a laser, and the metallic TaSe2 flakes were stacked on doped WSe2 as electrodes. Doping the contact areas decreases the depletion width, while introducing the TaSe2 contact results in a lower Schottky barrier. This method significantly improves the electrical performance of the WSe2 FETs. The doped WSe2/TaSe2 contact exhibits an ultralow Schottky barrier height of 65 meV and a contact resistance of 11 kΩ·μm, which is a 50-fold reduction compared to the conventional Cr/Au contact. Our method offers a way on fabricating high-performance 2D FETs.

The micro thermoelectric device (m-TED) boasts features such as adjustable volume, straightforward structure, and precise, rapid temperature control, positioning it as the only current solution for managing the temperature of microelectronic systems. It is extensively utilized in 5G optical modules, laser lidars, and infrared detection. Nevertheless, as the size of the m-TED diminishes, the growing proportion of interface damages the device\'s operational reliability, constraining the advancement of the m-TED. In this study, we used commercially available bismuth telluride materials to construct the m-TED. The device\'s reliability was tested under various temperatures: -40, 85, 125, and 150 °C. By deconstructing and analyzing the devices that failed during the tests, we discovered that the primary cause of device failure was the degradation of the solder layer. Moreover, we demonstrated that encapsulating the device with polydimethylsiloxane (PDMS) could effectively delay the deterioration of its performance. This study sparks new insights into the service reliability of m-TEDs and paves the way for further optimizing device interface design and enhancing the device manufacturing process.