Abstract：
The potential of monolithic 3D integration technology is largely dependent on the enhancement of interconnect characteristics which can lead to thinner stacks, better heat dissipation, and reduced signal delays. Carbon materials such as graphene, characterized by sp2 hybridized carbons, are promising candidates for future interconnects due to their exceptional electrical, thermal conductivity and resistance to electromigration. However, a significant challenge lies in achieving low contact resistance between extremely thin semiconductor channels and graphitic materials. To address this issue, an innovative wafer-scale synthesis approach is proposed that enables low contact resistance between dry-transferred 2D semiconductors and the as-grown nanocrystalline graphitic interconnects. A hybrid graphitic interconnect with metal doping reduces the sheet resistance by 84% compared to an equivalent thickness metal film. Furthermore, the introduction of a buried graphitic contact results in a contact resistance that is 17 times lower than that of bulk metal contacts (>40 nm). Transistors with this optimal structure are used to successfully demonstrate a simple logic function. The thickness of active layer is maintained within sub-7 nm range, encompassing both channels and contacts. The ultrathin transistor and interconnect stack developed here, characterized by a readily etchable interlayer and low parasitic resistance, leads to heterogeneous integration of future 3D integrated circuits (ICs).
摘要：
单片3D集成技术的潜力在很大程度上取决于互连特性的增强，这可以导致更薄的堆叠，更好的散热，减少信号延迟。石墨烯等碳材料，以Sp2杂化碳为特征，由于其出色的电气特性，是未来互连的有希望的候选人，热导率和抗电迁移。然而,一个重要的挑战在于在极薄的半导体沟道和石墨材料之间实现低接触电阻。为了解决这个问题，我们提出了一种创新的晶圆级合成方法，该方法可以在干转移的2D半导体和生长的纳米晶石墨互连之间实现低接触电阻。与等效厚度的金属膜相比，具有金属掺杂的混合石墨互连将薄层电阻降低了84％。此外，掩埋石墨接触的引入导致接触电阻比块状金属接触(>40nm)低17倍。使用具有此最佳结构的晶体管成功地演示了简单的逻辑功能。活性层的厚度保持在7nm以下，包括渠道和联系人。在这项工作中开发的超薄晶体管和互连堆栈，其特点是易于蚀刻的中间层和低寄生电阻，导致未来3DIC的异构集成。本文受版权保护。保留所有权利。
