最近,量子元胞自动机(QCA)技术已经有了很多研究,因为它保证了低功耗,低复杂度,低延迟,和紧凑的空间。同时,近似算法,一种新的计算模式,简化了计算过程,并以低功耗的形式出现,算法电路的高性能设计方法。此外,XOR门已广泛用于数字设计,并且是可以在许多即将到来的技术中使用的基本构建块。全加器(FA)电路是QCA技术的关键组件,用于算术逻辑运算,包括减法,乘法,和分裂。对近似FA的设计进行了大量的研究,全减法器(FS),全加法器/减法器(FA/S),和基于XOR逻辑的4位纹波进位加法器(RCA),将它们作为创建基于QCA的算术电路的必要组件。本研究提出了三种新的有效的基于QCA的电路,基于XOR逻辑:近似FA,近似FS,近似FA/S,和近似4位纹波进位加法器(RCA)。有趣的是,有些设计的一侧有输入,另一侧有输出,使其更容易到达的组件,而不会被其他细胞包围,并导致更有效的电路设计。特别是,0.5个时钟相位的延迟,0.01μm2的面积,并且在近似FA和减法器设计中实现仅利用11个单元。同样,估计的FA/S设计显示0.5时钟相位延迟,0.01μm2面积,和用于实现的12个单元格。提出了使用64个QCA单元的近似4位RCA。这些设计的有效性通过QCADesigner程序的功能验证进行评估。根据仿真结果,这些提出的解决方案不仅功能良好,而且在速度和空间方面明显优于以前的想法。拟议的FA,FS,RCA设计比以前的最佳设计高出21%,21%,43%,分别,在细胞计数方面。
Recently, there has been a lot of research in Quantum Cellular Automata (QCA) technology because it promises low power consumption, low complexity, low latency, and compact space. Simultaneously, approximate arithmetic, a new paradigm in computing, streamlines the computational process and emerges as a low-power, high-performance design approach for arithmetic circuits. Furthermore, the XOR gate has been widely used in digital design and is a basic building block that can be used in many upcoming technologies. The full adder (FA) circuit is a key component of QCA technology and is utilized in arithmetic
logic operations including subtraction, multiplication, and division. A great deal of research has been done on the design of approximate FA, full subtractor (FS), full adder/subtractor (FA/S), and 4-bit ripple carry adder (RCA) based on XOR
logic, establishing them as essential components in the creation of QCA-based arithmetic circuits. This study presents three new and effective QCA-based circuits, based on XOR
logic: an approximate FA, an approximate FS, an approximate FA/S, and an approximate 4-bit ripple carry adder (RCA). Interestingly, some designs have inputs on one side and outputs on the other, making it easier to reach the components without being encircled by other cells and leading to a more effective circuit design. In particular, a delay of 0.5 clock phases, an area of 0.01 μm2, and implementation utilizing just 11 cells was accomplished in the approximate FA and subtractor designs. In a similar vein, the estimated FA/S designs showed 0.5 clock phase delay, 0.01 μm2 area, and 12 cells used for implementation. An approximate 4-bit RCA is proposed using 64 QCA cells. The effectiveness of these designs is evaluated through functional verification with the QCADesigner program. According to simulation results, these proposed solutions not only function well but significantly outperform previous ideas in terms of speed and space. The proposed FA, FS, and RCA designs surpassed the previous best designs by 21%, 21%, and 43%, respectively, in terms of cell count.