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Abstract：
On-chip electrostatic discharge (ESD) protection is required for all integrated circuits (ICs). Conventional on-chip ESD protection relies on in-Si PN junction-based device structures for ESD. However, such in-Si PN-based ESD protection solutions pose significant challenges related to ESD protection design overhead, including parasitic capacitance, leakage current, and noises, as well as large chip area consumption and difficulty in IC layout floor planning. The design overhead effects of ESD protection devices are becoming unacceptable to modern ICs as IC technologies continuously advance, which is an emerging design-for-reliability challenge for advanced ICs. In this paper, we review the concept development of disruptive graphene-based on-chip ESD protection comprising a novel graphene nanoelectromechanical system (gNEMS) ESD switch and graphene ESD interconnects. This review discusses the simulation, design, and measurements of the gNEMS ESD protection structures and graphene ESD protection interconnects. The review aims to inspire non-traditional thinking for future on-chip ESD protection.
摘要：
所有集成电路(IC)都需要片上静电放电(ESD)保护。常规的片上ESD保护依赖于用于ESD的基于Si内PN结的器件结构。然而,这种基于SiPN的ESD保护解决方案带来了与ESD保护设计开销相关的重大挑战，包括寄生电容，漏电流,和噪音，以及芯片面积消耗大、IC布局层规划难度大。随着IC技术的不断进步，ESD保护器件的设计开销效应对现代IC变得不可接受，这是先进IC的一个新兴的可靠性设计挑战。在本文中,我们回顾了基于石墨烯的破坏性芯片ESD保护的概念发展，包括新型石墨烯纳米机电系统（gNEMS）ESD开关和石墨烯ESD互连。这篇评论讨论了模拟，设计,和测量gNEMSESD保护结构和石墨烯ESD保护互连。该评论旨在激发对未来片上ESD保护的非传统思考。
