The high-temperature stability of RuAl-based electrodes for application in microelectronic devices is analyzed for long-term duration. The electrodes are prepared on Ca3TaGa3Si2O14 (CTGS) substrates using SiO2 and Al-N-O cover and barrier layers as oxidation protection. The samples are annealed at 600, 700, or 800 °C in air for 192 h. Minor degradation is observed after thermal loading at 700 °C. The annealing at 800 °C for 192 h leads to a partial oxidation of the Al in the extended contact pad and to a complete oxidation of the Al within the structured interconnect electrodes. The different degradation of the interconnect electrodes and the contact pads is caused by their different lateral dimensions. In summary, long-term high-temperature stability is demonstrated up to at least 700 °C in air. Less oxidizing atmospheres should allow the application at higher temperatures and for a significantly longer duration.

Interconnect materials play the critical role of routing energy and information in integrated circuits. However, established bulk conductors, such as copper, perform poorly when scaled down beyond 10 nm, limiting the scalability of logic devices. Here, a multi-objective search is developed, combined with first-principles calculations, to rapidly screen over 15,000 materials and discover new interconnect candidates. This approach simultaneously optimizes the bulk electronic conductivity, surface scattering time, and chemical stability using physically motivated surrogate properties accessible from materials databases. Promising local interconnects are identified that have the potential to outperform ruthenium, the current state-of-the-art post-Cu material, and also semi-global interconnects with potentially large skin depths at the GHz operation frequency. The approach is validated on one of the identified candidates, CoPt, using both ab initio and experimental transport studies, showcasing its potential to supplant Ru and Cu for future local interconnects.

The integration of carbon nanostructures with semiconductor nanowires holds significant potential for energy-efficient integrated circuits. However, achieving precise control over the positioning and stability of these interconnections poses a major challenge. This study presents a method for the controlled growth of carbon nanofibers (CNFs) on vertically aligned indium arsenide (InAs) nanowires. The CNF/InAs hybrid structures, synthesized using chemical vapor deposition (CVD), were successfully produced without compromising the morphology of the pristine nanowires. Under optimized conditions, preferential growth of the carbon nanofibers in the direction perpendicular to the InAs nanowires was observed. Moreover, when the CVD process employed iron as a catalyst, an increased growth rate was achieved. With and without the presence of iron, carbon nanofibers nucleate preferentially on the top of the InAs nanowires, indicating a tip growth mechanism presumably catalysed by a gold-indium alloy that selectively forms in that region. These results represent a compelling example of controlled interconnections between adjacent InAs nanowires formed by carbon fibers.

Stretchable interconnects with miniature widths are vital for the high-density integration of deformable electronic components on a single substrate for targeted data logic or storage functions. However, it is still challenging to attain high-resolution patternability of stretchable conductors with robust circuit fabrication capability. Here, we report a self-assembled silver nanofilm firmly interlocked by an elastomeric nanodielectric that can be photolithographically patterned into microscale features while preserving high stretchability and conductivity. Both silver and dielectric nanofilms are fabricated by layer-by-layer assembly, ensuring wafer-scale uniformity and meticulous control of thicknesses. Without any thermal annealing, the as-fabricated nanofilms from silver nanoparticles (AgNPs) exhibit conductivity of 1.54 × 106 S m-1 and stretchability of ∼200%, which is due to the impeded crack propagation by the underlying PU nanodielectrics. Furthermore, it is revealed that AgNP microstrips defined by photolithography show higher stretchability when their widths are downscaled to 100 μm owing to confined cracks. However, further scaling restricts the stretchability, following the early development of cracks cutting across the strip. In addition, the resistance change of these silver interconnects can be decreased using serpentine architectures. As a demonstration, these self-assembled interconnects are used as stretchable circuit boards to power LEDs.

With the continuous shrinkage of integrated circuit (IC) dimensions, traditional copper interconnect technology is gradually unable to meet the requirements for performance improvement. Carbon nanotubes have gained widespread attention and research as a potential alternative to copper, due to their excellent electrical and mechanical properties. Among various methods for producing carbon nanotubes, chemical vapor deposition (CVD) has the advantages of mild reaction conditions, low cost, and simple reaction operations, making it the most promising approach to achieve compatibility with integrated circuit manufacturing processes. Combined with through silicon via (TSV), direct application of CVD-grown carbon nanotubes in IC interconnects can be achieved. In this article, based on the above background, we focus on discussing some of the main challenges and developments in the application of CVD-grown carbon nanotubes in IC interconnects, including low-temperature CVD, metallicity enrichment, and contact resistance.

On-chip electrostatic discharge (ESD) protection is required for all integrated circuits (ICs). Conventional on-chip ESD protection relies on in-Si PN junction-based device structures for ESD. However, such in-Si PN-based ESD protection solutions pose significant challenges related to ESD protection design overhead, including parasitic capacitance, leakage current, and noises, as well as large chip area consumption and difficulty in IC layout floor planning. The design overhead effects of ESD protection devices are becoming unacceptable to modern ICs as IC technologies continuously advance, which is an emerging design-for-reliability challenge for advanced ICs. In this paper, we review the concept development of disruptive graphene-based on-chip ESD protection comprising a novel graphene nanoelectromechanical system (gNEMS) ESD switch and graphene ESD interconnects. This review discusses the simulation, design, and measurements of the gNEMS ESD protection structures and graphene ESD protection interconnects. The review aims to inspire non-traditional thinking for future on-chip ESD protection.

UV-induced photoluminescence of organosilica films with ethylene and benzene bridging groups in their matrix and terminal methyl groups on the pore wall surface was studied to reveal optically active defects and understand their origin and nature. The careful selection of the film\'s precursors and conditions of deposition and curing and analysis of chemical and structural properties led to the conclusion that luminescence sources are not associated with the presence of oxygen-deficient centers, as in the case of pure SiO2. It is shown that the sources of luminescence are the carbon-containing components that are part of the low-k-matrix, as well as the carbon residues formed upon removal of the template and UV-induced destruction of organosilica samples. A good correlation between the energy of the photoluminescence peaks and the chemical composition is observed. This correlation is confirmed by the results obtained by the Density Functional theory. The photoluminescence intensity increases with porosity and internal surface area. The spectra become more complicated after annealing at 400 °C, although Fourier transform infrared spectroscopy does not show these changes. The appearance of additional bands is associated with the compaction of the low-k matrix and the segregation of template residues on the surface of the pore wall.

Mo(001) and Mo(011) layers with thickness d = 4-400 nm are sputter-deposited onto MgO(001) and α-Al2O3(112¯0) substrates and their resistivity is measured in situ and ex situ at room temperature and 77 K in order to quantify the resistivity size effect. Both Mo(001) and Mo(011) layers are epitaxial single crystals and exhibit a resistivity increase with decreasing d due to electron surface scattering that is well described by the classical Fuchs and Sondheimer model. Data fitting yields room temperature effective electron mean free paths λ*= 14.4 ± 0.3 and 11.7 ± 0.3 nm, respectively, indicating an anisotropy with a smaller resistivity size effect for the Mo(011) orientation. This is attributed to a smaller average Fermi velocity component perpendicular to (011) surfaces, causing less surface scattering and a suppressed resistivity size effect. First-principles electronic structure calculations in combination with Boltzmann transport simulations predict an orientation dependent transport with a more pronounced resistivity increase for Mo(001) than Mo(011). This is in agreement with the measurements, confirming the effect of the Fermi surface shape on the thin-film resistivity. The predicted anisotropy λ001*/λ011* = 1.57 is in reasonable agreement with 1.66 and 1.23 measured at 77 and 295 K. The overall results indicate that the resistivity size effect in Mo is relatively small, with a measured product of the bulk resistivity times the effective electron mean free path ρoλ* = (7.7 ± 0.3) and (6.2 ± 0.2) × 10-16 Ωm2 for Mo(001) and Mo(011) layers. The latter value is in excellent agreement with the first-principles-predicted ρoλ = 5.99 × 10-16 Ωm2 and is 10% and 40% smaller than the reported measured ρoλ for Cu and W, respectively, indicating the promise of Mo as an alternate conductor for narrow interconnects.

Network on chip (NoC) is the main solution to the communication bandwidth of a multi-processor system on chip (MPSoC). NoC also brings more route requirements and is highly prone to errors caused by crosstalk. Crosstalk has become a major design problem in deep-submicron NoC communication design. Hence, a crosstalk error model and corresponding reliable system with error correction code (ECC) are required to make NoC communication reliable. In this paper, a reliability system evaluation model (RSE) of NoC communication with analysis from backend to frontend has been proposed. In the backend, a crosstalk error rate model (CER) is established with a three-wire RLC coupling model and timing constraints. The CER is used to establish functional relations between interconnect spacing, length and signal frequency, and test system reliability. In the frontend, a reliability system performance model (RSP) is established with a CER, reliability method cost and bandwidth. The RSE summarizes the frontend and backend model. In order to verify the RSE model, we propose a reliability system with a hybrid automatic repeat request technique (RSHARQ). Simulation demonstrates that the CER model is close to real circuit design. Through the CER and RSP model, the performance of RSHARQ could be simulated.

The increasing resistance of copper (Cu) interconnects for decreasing dimensions is a major challenge in continued downscaling of integrated circuits beyond the 7 nm technology node as it leads to unacceptable signal delays and power consumption in computing. The resistivity of Cu increases due to electron scattering at surfaces and grain boundaries at the nanoscale. Topological semimetals, owing to their topologically protected surface states and suppressed electron backscattering, are promising candidates to potentially replace current Cu interconnects. Here, we report the unprecedented resistivity scaling of topological metal molybdenum phosphide (MoP) nanowires, and it is shown that the resistivity values are superior to those of nanoscale Cu interconnects <500 nm2 cross-section areas. The cohesive energy of MoP suggests better stability against electromigration, enabling a barrier-free design . MoP nanowires are more resistant to surface oxidation than the 20 nm thick Cu. The thermal conductivity of MoP is comparable to those of Ru and Co. Most importantly, it is demonstrated that the dimensional scaling of MoP, in terms of line resistance versus total cross-sectional area, is competitive to those of effective Cu with barrier/liner and barrier-less Ru, suggesting MoP is an attractive alternative for the scaling challenge of Cu interconnects.