On-chip electrostatic discharge (ESD) protection is required for all integrated circuits (ICs). Conventional on-chip ESD protection relies on in-Si PN junction-based device structures for ESD. However, such in-Si PN-based ESD protection solutions pose significant challenges related to ESD protection design overhead, including parasitic capacitance, leakage current, and noises, as well as large chip area consumption and difficulty in IC layout floor planning. The design overhead effects of ESD protection devices are becoming unacceptable to modern ICs as IC technologies continuously advance, which is an emerging design-for-reliability challenge for advanced ICs. In this paper, we review the concept development of disruptive graphene-based on-chip ESD protection comprising a novel graphene nanoelectromechanical system (gNEMS) ESD switch and graphene ESD interconnects. This review discusses the simulation, design, and measurements of the gNEMS ESD protection structures and graphene ESD protection interconnects. The review aims to inspire non-traditional thinking for future on-chip ESD protection.

In this work, a new low voltage-triggered silicon-controlled rectifier named MTSCR is realized in a 65 nm CMOS process for low voltage-integrated circuits electrostatic discharge (ESD) protections. The MTSCR incorporates an external NMOSs-string, which drives the internal NMOS (INMOS) of MTSCR to turn on, and then the INMOS drive SCR structure to turn on. Compared with the existing low trigger voltage (Vt1) ESD component named diodes-string-triggered SCR (DTSCR), the MTSCR can realize the same low Vt1 characteristic but less area penalty of ~44.3% reduction. The results of the transmission line pulsing (TLP) measurement shows that the MTSCR possesses above 2.42 V holding voltage (Vh) and a low Vt1 of ~5.03 V, making it very suitable for the ESD protections for 1.8 V input/output (I/O) ports in CMOS technologies.

As the demands for improved performance of integrated circuit (IC) chips continue to increase, while technology scaling driven by Moore\'s law is becoming extremely challenging, if not impractical or impossible, heterogeneous integration (HI) emerges as an attractive pathway to further enhance performance of Si-based complementary metal-oxide-semiconductor (CMOS) chips. The underlying basis for using HI technologies and structures is that IC performance goes well beyond classic logic functions; rather, functionalities and complexity of smart chips span across the full information chain, including signal sensing, conditioning, processing, storage, computing, communication, control, and actuation, which are required to facilitate comprehensive human-world interactions. Therefore, HI technologies can bring in more function diversifications to make system chips smarter within acceptable design constraints, including costs. Over the past two decades or so, a large number of HI technologies have been explored to increase heterogeneities in materials, technologies, devices, circuits, and system architectures, making it practically impossible to provide one single comprehensive review of everything in the field in one paper. This article chooses to offer a topical overview of selected HI structures that have been validated in CMOS platforms, including a stacked-via vertical magnetic-cored inductor structure in CMOSs, a metal wall structure in the back end of line (BEOL) of CMOSs to suppress global flying noises, an above-IC graphene nano-electromechanical system (NEMS) switch and nano-crossbar array electrostatic discharge (ESD) protection structure, and graphene ESD interconnects.

Low-voltage-triggered silicon-controlled rectifier (LVTSCR) is expected to provide an electrostatic discharge (ESD) protection for a low-voltage integrated circuit. However, it is normally vulnerable to the latch-up effect due to its extremely low holding voltage. In this paper, a novel LVTSCR embedded with an extra p-type MOSFET called EP-LVTSCR has been proposed and verified in a 28-nm CMOS technology. The proposed device possesses a lower trigger voltage of ~ 6.2 V and a significantly higher holding voltage of ~ 5.5 V with only 23% degradation of the failure current under the transmission line pulse test. It is also shown that the EP-LVTSCR operates with a lower turn-on resistance of ~ 1.8 Ω as well as a reliable leakage current of ~ 1.8 nA measured at 3.63 V, making it suitable for ESD protections in 2.5 V/3.3 V CMOS processes. Moreover, the triggering mechanism and conduction characteristics of the proposed device were explored and demonstrated with TCAD simulation.