PDF(Pubmed)
Abstract：
As the demands for improved performance of integrated circuit (IC) chips continue to increase, while technology scaling driven by Moore\'s law is becoming extremely challenging, if not impractical or impossible, heterogeneous integration (HI) emerges as an attractive pathway to further enhance performance of Si-based complementary metal-oxide-semiconductor (CMOS) chips. The underlying basis for using HI technologies and structures is that IC performance goes well beyond classic logic functions; rather, functionalities and complexity of smart chips span across the full information chain, including signal sensing, conditioning, processing, storage, computing, communication, control, and actuation, which are required to facilitate comprehensive human-world interactions. Therefore, HI technologies can bring in more function diversifications to make system chips smarter within acceptable design constraints, including costs. Over the past two decades or so, a large number of HI technologies have been explored to increase heterogeneities in materials, technologies, devices, circuits, and system architectures, making it practically impossible to provide one single comprehensive review of everything in the field in one paper. This article chooses to offer a topical overview of selected HI structures that have been validated in CMOS platforms, including a stacked-via vertical magnetic-cored inductor structure in CMOSs, a metal wall structure in the back end of line (BEOL) of CMOSs to suppress global flying noises, an above-IC graphene nano-electromechanical system (NEMS) switch and nano-crossbar array electrostatic discharge (ESD) protection structure, and graphene ESD interconnects.
摘要：
随着提高集成电路(IC)芯片性能的需求不断增加,虽然由摩尔定律驱动的技术扩展变得极具挑战性，如果不是不切实际或不可能，异质集成(HI)作为进一步增强硅基互补金属氧化物半导体(CMOS)芯片性能的有吸引力的途径出现。使用HI技术和结构的基础是IC性能远远超出经典逻辑功能；智能芯片的功能和复杂性跨越整个信息链，包括信号传感，conditioning,processing,storage,计算，通信,control,和致动，这是促进人类与世界全面互动所必需的。因此,HI技术可以带来更多的功能多样化，使系统芯片在可接受的设计约束下更加智能，包括成本。在过去的二十年左右，已经探索了大量的HI技术来增加材料的异质性，技术,设备,电路，和系统架构，这使得几乎不可能在一篇论文中对该领域的所有内容进行一次全面的审查。本文选择提供已在CMOS平台中验证的选定HI结构的主题概述，包括CMOS中的堆叠式垂直磁芯电感器结构，CMOSs后端（BEOL）的金属壁结构，以抑制全局飞行噪声，IC以上的石墨烯纳米机电系统（NEMS）开关和纳米交叉阵列静电放电（ESD）保护结构，和石墨烯ESD互连。
