本简介提出了一种具有收敛加速技术的流水线SAR模数转换器(ADC)中与信号无关的背景校准。为了实现信号独立性,辅助电容器阵列CA被引入以在采样阶段预注入伪随机噪声(PN),以抵消在转换阶段校准电容器的相反PN注入。和CA还用于在转换阶段实现校准电容器的D/A功能。这样,不管信号是什么,即使使用PN注入,残留物净空也保持不变。此外,例如,第一子ADC被设计为具有扩展的转换位,以在递送第一级所需的转换位之后量化其自身的残余。之后,此结果被提供给校准算法,以减少信号分量并加速收敛。基于模拟,信噪比和失真比(SNDR)和无杂散动态范围(SFDR)从45.3dB和56.4dB提高到68.2dB和88.4dB,分别,校准后。此外,用加速技术,收敛周期从1.7×108减少到5.8×106。此外,无论输入信号是否为直流,正弦波或带限白噪声,校准工作正常。
This brief proposes a signal-independent background calibration in pipeline-SAR analog-to-digital converters (ADCs) with a convergence-accelerated technique. To achieve signal independence, an auxiliary capacitor array CA is introduced to pre-inject a pseudo-random noise (PN) in the sampling phase to cancel out the opposite PN injection of the calibrated capacitor in the conversion phase, and CA is also used to realize the D/A function of the calibrated capacitor in the conversion phase. In this way, no matter what the signal is, the residue headroom remains unchanged even with PN injection. Moreover, the first sub-ADC is designed with extended conversion bits to quantize its own residue after delivering the conversion bits required by the first stage. Afterwards, this result is provided to the calibration algorithm to reduce the signal component and accelerate the convergence. Based on the simulation, the signal-to-noise and distortion ratio (SNDR) and spur-free dynamic range (SFDR) improve from 45.3 dB and 56.4 dB to 68.2 dB and 88.4 dB, respectively, after calibration. In addition, with the acceleration technique, convergence cycles decrease from 1.7 × 108 to 5.8 × 106. Moreover, no matter whether the input signal is DC, sine wave or band-limited white noise, the calibration all works normally.