Identifying underperforming photovoltaic (PV) modules is crucial to ensure optimal energy production and financial returns, as well as preventing potential safety hazards in case of severe damage. To this aim, current-voltage (I-V) curve tracing can be employed as in situ monitoring technique for the early detection of faults. In this paper, we introduce a novel low-cost, microcontroller-based I-V tracer for the diagnosis of individual PV modules. The tool features a unique power conditioning circuit, facilitating accurate data acquisition under static conditions as well as the even distribution of the measured points along the I-V curve. A specific active disconnecting circuit enables in situ and on-line measurement without interrupting the string power generation. The designed prototype is used to characterize a set of PV modules under real operating conditions. The measured I-V curves exhibit expected trends, with the measured data closely matching theoretical values and an estimated mean relative error less than 3%.

Crop diseases can significantly affect various aspects of crop cultivation, including crop yield, quality, production costs, and crop loss. The utilization of modern technologies such as image analysis via machine learning techniques enables early and precise detection of crop diseases, hence empowering farmers to effectively manage and avoid the occurrence of crop diseases. The proposed methodology involves the use of modified MobileNetV3Large model deployed on edge device for real-time monitoring of grape leaf disease while reducing computational memory demands and ensuring satisfactory classification performance. To enhance applicability of MobileNetV3Large, custom layers consisting of two dense layers were added, each followed by a dropout layer, helped mitigate overfitting and ensured that the model remains efficient. Comparisons among other models showed that the proposed model outperformed those with an average train and test accuracy of 99.66% and 99.42%, with a precision, recall, and F1 score of approximately 99.42%. The model was deployed on an edge device (Nvidia Jetson Nano) using a custom developed GUI app and predicted from both saved and real-time data with high confidence values. Grad-CAM visualization was used to identify and represent image areas that affect the convolutional neural network (CNN) classification decision-making process with high accuracy. This research contributes to the development of plant disease classification technologies for edge devices, which have the potential to enhance the ability of autonomous farming for farmers, agronomists, and researchers to monitor and mitigate plant diseases efficiently and effectively, with a positive impact on global food security.

This article describes constructing an embedded system for a painting art and style presentation platform, achieving the automatic integration of digital painting art with traditional art design. The frontend components are designed using the Bootstrap framework, with Django as the web development framework and TensorFlow architecture integrated into the code. Furthermore, the Inception module and residual connections are introduced to optimize the visual geometry group (VGG) network for recognizing and analyzing image texture features. Compared to other models, experimental results indicate that the proposed model demonstrates a 2.6% increase in image style classification accuracy, reaching 87.34% and 95.33% in architectural and landscape image classification, respectively. The system\'s operational outcomes reveal that the proposed platform alleviates the burden on the logical function modules of the system, enhances scalability, and promotes the automated fusion of digital painting art with traditional art design expression.

A novel High-Frequency Electric Energy Metering System to inspect non-conventional features that may be relevant for studying real-time energy disaggregation and control of household appliances is presented. Integration of a data acquisition and control board, designed and built to be assembled with an Arduino Due, with the M90E36A Demo Board, allows for flexible and configurable electrical energy measurements. A key feature is that up to 4 current channels can be measured synchronously. On the one hand, samples can be obtained and processed by the M90E36A IC internal Digital Signal Processor at 3 Hz in the time domain and 2 Hz in the frequency domain. On the other hand, the M90E36A IC direct access memory mode can be operated, allowing 8 kHz pure voltage and current signals to be obtained. Finally, integration with Raspberry Pi allows to design and incorporate a custom signal processor into the study. Additionally, in this article, an application example is presented where the variation of the residual harmonic components of a household appliance is obtained.

The branch prediction units (BPUs) generally have security vulnerabilities, which can be used by attackers to tamper with the branches, and the existing protection methods cannot defend against these attacks. Therefore, this article proposes a hardware security protection method for conditional branches of embedded systems. This method calculates the number of branch target buffer (BTB) updates every 80 clock cycles. If the number exceeds the set threshold, the BTB will be locked and prevent any process from tampering with the BTB entries, thereby resisting branch prediction analysis (BPA) attacks. Moreover, to prevent attackers from stealing the critical information of branches, the method designs the hybrid arbiter physical unclonable function (APUF) circuit to encrypt and decrypt the directions, addresses, and indexes of branches. This circuit combines the advantages of double APUF and Feed-Forward APUF, which can enhance the randomness of output response and resist machine learning attacks. If attackers still successfully tamper with the branches and disrupt the control flow integrity (CFI), this method detects tampering with the instruction codes, jump addresses, and jump directions in a timely manner through dynamic and static label comparison. The proposed method is implemented and tested on FPGA. The experimental results show that this method can achieve fine-grained security protection for conditional branches, with about 5.4% resource overhead and less than 5.5% performance overhead.

This research presents an experimental electric vehicle developed at the Tecnológico Nacional de México Celaya campus. It was decided to use a golf cart-type gasoline vehicle as a starting point. Initially, the body was removed, and the vehicle was electrified, meaning its engine was replaced with an electric one. Subsequently, sensors used to measure the vehicle states were placed, calibrated, and instrumented. Additionally, a mathematical model was developed along with a strategy for the parametric identification of this model. A communication scheme was implemented consisting of four slave devices responsible for controlling the accelerator, brake, steering wheel, and measuring the sensors related to odometry. The master device is responsible for communicating with the slaves, displaying information on a screen, creating a log, and implementing trajectory tracking techniques based on classical, geometric, and predictive control. Finally, the performance of the control algorithms implemented on the experimental prototype was compared in terms of tracking error and control input across three different types of trajectories: lane change, right-angle curve, and U-turn.

Smart algorithms for gait kinematic motion prediction in wearable assistive devices including prostheses, bionics, and exoskeletons can ensure safer and more effective device functionality. Although embedded systems can support the use of smart algorithms, there are important limitations associated with computational load. This poses a tangible barrier for models with increased complexity that demand substantial computational resources for superior performance. Forecasting through Recurrent Topology (FReT) represents a computationally lightweight time-series data forecasting algorithm with the ability to update and adapt to the input data structure that can predict complex dynamics. Here, we deployed FReT on an embedded system and evaluated its accuracy, computational time, and precision to forecast gait kinematics from lower-limb motion sensor data from fifteen subjects. FReT was compared to pretrained hyperparameter-optimized NNET and deep-NNET (D-NNET) model architectures, both with static model weight parameters and iteratively updated model weight parameters to enable adaptability to evolving data structures. We found that FReT was not only more accurate than all the network models, reducing the normalized root-mean-square error by almost half on average, but that it also provided the best balance between accuracy, computational time, and precision when considering the combination of these performance variables. The proposed FReT framework on an embedded system, with its improved performance, represents an important step towards the development of new sensor-aided technologies for assistive ambulatory devices.

While Siamese object tracking has witnessed significant advancements, its hard real-time behaviour on embedded devices remains inadequately addressed. In many application cases, an embedded implementation should not only have a minimal execution latency, but this latency should ideally also have zero variance, i.e., be predictable. This study aims to address this issue by meticulously analysing real-time predictability across different components of a deep-learning-based video object tracking system. Our detailed experiments not only indicate the superiority of Field-Programmable Gate Array (FPGA) implementations in terms of hard real-time behaviour but also unveil important time predictability bottlenecks. We introduce dedicated hardware accelerators for key processes, focusing on depth-wise cross-correlation and padding operations, utilizing high-level synthesis (HLS). Implemented on a KV260 board, our enhanced tracker exhibits not only a speed up, with a factor of 6.6, in mean execution time but also significant improvements in hard real-time predictability by yielding 11 times less latency variation as compared to our baseline. A subsequent analysis of power consumption reveals our approach\'s contribution to enhanced power efficiency. These advancements underscore the crucial role of hardware acceleration in realizing time-predictable object tracking on embedded systems, setting new standards for future hardware-software co-design endeavours in this domain.

Field Programmable Gate Arrays (FPGAs) are integrated circuits that can be configured by the user after manufacturing, making them suitable for customized hardware prototypes, a feature not available in general-purpose processors in Application Specific Integrated Circuits (ASIC). In this paper, we review the vast Machine Learning (ML) algorithms implemented on FPGAs to increase performance and capabilities in healthcare technology over 2001-2023. In particular, we focus on real-time ML algorithms targeted to FPGAs and hybrid System-on-a-chip (SoC) FPGA architectures for biomedical applications. We discuss how previous works have customized and optimized their ML algorithm and FPGA designs to address the putative embedded systems challenges of limited memory, hardware, and power resources while maintaining scalability to accommodate different network sizes and topologies. We provide a synthesis of articles implementing classifiers and regression algorithms, as they are significant algorithms that cover a wide range of ML algorithms used for biomedical applications. This article is written to inform the biomedical engineering and FPGA design communities to advance knowledge of FPGA-enabled ML accelerators for biomedical applications.

Portable sensor systems are usually based on microcontrollers and/or Field-Programmable Gate Arrays (FPGAs) that are interfaced with sensors by means of an Analog-to-Digital converter (ADC), either integrated in the computing device or external. An alternative solution is based on the direct connection of the sensors to the digital input port of the microcontroller or FPGA. This solution is particularly interesting in the case of devices not integrating an internal ADC or featuring a small number of ADC channels. In this paper, a technique is presented to directly interface sensors with analog voltage output to the digital input port of a microcontroller or FPGA. The proposed method requires only a few passive components and is based on the measurements of the duty cycle of a digital square-wave signal. This technique was investigated by means of circuit simulations using LTSpice and was implemented in a commercial low-cost FPGA device (Gowin GW1NR-9). The duty cycle of the square-wave signal features a good linear correlation with the analog voltage to be measured. Thus, a look-up table to map the analog voltage values to the measured duty cycle is not required with benefits in terms of memory occupation. The experimental results on the FPGA device have shown that the analog voltage can be measured with a maximum accuracy of 1.09 mV and a sampling rate of 9.75 Hz. The sampling rate can be increased to 31.35 Hz and 128.31 Hz with an accuracy of 1.61 mV and 2.68 mV, respectively.