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Abstract：
The article presents the analysis, design, and low-cost implementation of application-specific AD converters for M-sequence-based UWB applications to minimize and integrate the whole UWB sensor system. Therefore, the main goal of this article is to integrate the AD converter\'s own design with the UWB analog part into the system-in-package (SiP) or directly into the system-on-a-chip (SoC), which cannot be implemented with commercial AD converters, or which would be disproportionately expensive. Based on the current and used UWB sensor system requirements, to achieve the maximum possible bandwidth in the proposed semiconductor technology, a parallel converter structure is designed and presented in this article. Moreover, 5-bit and 4-bit parallel flash AD converters were initially designed as part of the research and design of UWB M-sequence radar systems for specific applications, and are briefly introduced in this article. The requirements of the newly proposed specific UWB M-sequence systems were established based on the knowledge gained from these initial designs. After thorough testing and evaluation of the concept of the early proposed AD converters for these specific UWB M-sequence systems, the design of a new AD converter was initiated. After confirming sufficient characteristics based on the requirements of UWB M-sequence systems for specific applications, a 7-bit AD converter in low-cost 0.35 µm SiGe BiCMOS technology from AMS was designed, fabricated, and presented in this article. The proposed 7-bit AD converter achieves the following parameters: ENOB = 6.4 bits, SINAD = 38 dB, SFDR = 42 dBc, INL = ±2-bit LSB, and DNL = ±1.5 LSB. The maximum sampling rate reaches 1.4 Gs/s, the power consumption at 20 Ms/s is 1050 mW, and at 1.4 Gs/s is 1290 mW, with a power supply of -3.3 V.
摘要：
本文提出了分析，设计,以及针对基于M序列的UWB应用的特定应用AD转换器的低成本实现，以最小化和集成整个UWB传感器系统。因此,本文的主要目标是将AD转换器自己的设计与UWB模拟部分集成到系统级封装（SiP）或直接集成到系统级芯片（SoC）中，不能用商用AD转换器实现，或者会不成比例地昂贵。根据目前使用的UWB传感器系统的要求,为了在拟议的半导体技术中实现最大可能的带宽，本文设计并介绍了一种并联变换器结构。此外，5位和4位并行闪存AD转换器最初被设计为用于特定应用的UWBM序列雷达系统的研究和设计的一部分，并在本文中进行了简要介绍。根据从这些初始设计中获得的知识，建立了新提出的特定UWBM序列系统的要求。在对这些特定UWBM序列系统的早期提出的AD转换器的概念进行全面测试和评估之后，设计了一个新的AD转换器。在根据特定应用的UWBM序列系统的要求确认足够的特性之后，采用AMS低成本0.35µmSiGeBiCMOS技术设计了7位AD转换器，制作,并在本文中介绍。建议的7位AD转换器实现以下参数：ENOB=6.4位，SINAD=38dB,SFDR=42dBc,INL=±2位LSB，DNL=±1.5LSB。最大采样率达到1.4Gs/s，20Ms/s时的功耗为1050mW，在1.4Gs/s时为1290mW，电源为-3.3V。
