Abstract：
Ferroelectric transistors are considered promising for next-generation 3D NAND technology due to their lower power consumption and faster operation compared to conventional charge-trap flash memories. However, ensuring their suitability for such applications requires a thorough investigation of array-scale reliability. This study specifically examines the suitability of hafnia-based ferroelectric transistors for advanced 3D NAND applications, with a specific focus on establishing a disturb-free voltage scheme to ensure the reliability of ferroelectric transistors within the array. Our key finding highlights the crucial role of optimal pass voltage in achieving disturb-free operation in both 2D and 3D ferroelectric NAND arrays. Additionally, the study indicates that read disturb remains negligible when an appropriate read voltage is applied. These insights provide a practical strategy for achieving reliable operation in 2D and 3D ferroelectric NAND, highlighting the potential of hafnia-based ferroelectric materials to meet the evolving requirements of high-density and reliable NAND flash memory applications.
摘要：
铁电晶体管被认为是下一代3DNAND技术的前景，因为与传统的电荷陷阱闪存相比，它们具有更低的功耗和更快的操作。然而,确保它们适合此类应用需要对阵列规模的可靠性进行彻底的调查。这项研究专门研究了基于hafnia的铁电晶体管在高级3DNAND应用中的适用性，特别关注建立无干扰电压方案，以确保阵列内铁电晶体管的可靠性。我们的关键发现强调了最佳通过电压在2D和3D铁电NAND阵列中实现无干扰操作的关键作用。此外,研究表明，当施加适当的读取电压时，读取干扰仍然可以忽略不计。这些见解为实现2D和3D铁电NAND的可靠操作提供了实用策略，强调了氧化铪基铁电材料的潜力，以满足高密度和可靠的NAND闪存应用的不断发展的要求。
