Abstract：
The application requirements of high frame rate CMOS image sensors (CIS) in the industry have not been satisfied due to the speed limitations in traditional single-slope and serial two-step analog-to-digital converters (ADCs). In this paper, a high-speed fully differential two-step ADC design method for CIS was proposed. The proposed method was based on differential ramp and time-to-digital conversion (TDC) technology. A parallel conversion mode was formed that is different from serial conversion, and the robustness of the system was ensured due to the existence of differential ramps. Aiming at the inconsistency between traditional TDC technology and single-slope ADC, a TDC technology based on level coding was proposed. The proposed technology achieves the TDC in the last clock cycle of analog-to-digital conversion, and realized a two-step conversion process at another level. This paper presents a complete circuit design, layout design, and test verification of the proposed design method based on the 55 nm 1P4M CMOS experimental platform. Under the design environment of the analog voltage of 3.3 V, the digital voltage of 1.2 V, the clock frequency of 100 MHz, and a dynamic input range of 1.6 V, this design was a 12-bit ADC with a conversion time of 480 ns, column-level power consumption of 62 μW, differential nonlinearity (DNL) of +0.6/-0.6 LSB, and integral nonlinearity (INL) of +1.2/-1.4 LSB. Furthermore, it achieved a signal-to-noise distortion ratio (SNDR) of 70.08 dB. The proposed design provided a large area array with a high frame rate, and compared with the existing advanced single-slope ADC, its conversion speed increased by more than 52%. It provides an effective solution for the implementation of high frame frequency CIS.
摘要：
由于传统的单斜率和串行两步模数转换器(ADC)中的速度限制,高帧速率CMOS图像传感器(CIS)在行业中的应用要求尚未得到满足。在本文中,提出了一种面向CIS的高速全差分两步ADC设计方法。该方法基于差分斜坡和时间数字转换(TDC)技术。形成了与串行转换不同的并行转换模式，并且由于差分斜坡的存在,保证了系统的鲁棒性。针对传统TDC技术与单斜率ADC的不一致,提出了一种基于电平编码的TDC技术。所提出的技术在模数转换的最后一个时钟周期中实现了TDC，并在另一个层面实现了两步转换过程。本文给出了一个完整的电路设计,布局设计，并基于55nm1P4MCMOS实验平台对所提设计办法停止了测试验证。在模拟电压为3.3V的设计环境下,1.2V的数字电压，100MHz的时钟频率,和1.6V的动态输入范围，该设计是一个转换时间为480ns的12位ADC，列级功耗为62μW，+0.6/-0.6LSB的微分非线性(DNL)，和+1.2/-1.4LSB的积分非线性(INL)。此外，它实现了70.08dB的信噪比(SNDR)。所提出的设计提供了具有高帧率的大面积阵列，与现有先进的单斜率ADC相比，其转换速度提高了52%以上。为实现高帧频率CIS提供了有效的解决方案。
