Abstract：
We propose a multidimensional reconciliation encoding algorithm based on a field-programmable gate array (FPGA) with variable data throughput that enables quantum key distribution (QKD) systems to be adapted to different throughput requirements. Using the circulatory structure, data flow in the most complex pipeline operation in the same time interval, which enables the structural multiplexing of the algorithm. We handle the calculation and storage of eight-dimensional matrices cleverly to conserve resources and increase data processing speed. In order to obtain the syndrome more efficiently, we designed a simplified algorithm according to the characteristics of the FPGA and parity-check matrix, which omits the unnecessary operation of matrix multiplication. The simplified algorithm could adapt to different rates. We validated the feasibility and high speed of the algorithm by implementing the multidimensional reconciliation encoding algorithm on a Xilinx Virtex-7 FPGA. Our simulation results show that the maximum throughput could reach 4.88 M symbols/s.
摘要：
我们提出了一种基于具有可变数据吞吐量的现场可编程门阵列（FPGA）的多维协调编码算法，该算法使量子密钥分发（QKD）系统能够适应不同的吞吐量要求。利用循环结构，在相同的时间间隔内最复杂的管道操作中的数据流，这实现了算法的结构复用。我们巧妙地处理八维矩阵的计算和存储，以节省资源并提高数据处理速度。为了更有效地获得综合征，根据FPGA和奇偶校验矩阵的特点,设计了一种简化算法,省略了矩阵乘法的不必要操作。简化算法可以适应不同的速率。通过在XilinxVirtex-7FPGA上实现多维协调编码算法,验证了该算法的可行性和高速性。我们的仿真结果表明，最大吞吐量可以达到4.88M符号/s。
